Print Page - Need help with some V850E code

I feel like this should be really simple, but something is tripping me up.

This code sets up my GP register. It's used for relative addressing elsewhere in the code.

Code:

movhi   0xFFFF, r0, gp
movea   0, gp, gp

R0 is a 'zero register'. IE, the contents are always zero.

Here's the descriptions for the two instructions.

Quote

MOVHI : Adds a word data, whose higher 16 bits are specified by the 16-bit immediate data and lower
16 bits are 0, to the word data of general register reg1 and stores the result in general register
reg2.

Quote

MOVEA: Adds the 16-bit immediate data, sign-extended to word length, to the word data of general
register reg1, and stores the result to general register reg2.

Based on the reference manual, I think GP should be 0xFFFF0000 when this is all done. Based on what little I've found on the web, this is just some compiler weirdness used to generate a 32 bit address.

Problem being, using this as a base for relative addressing later in the code generates invalid addresses.

So either there's some nuance of these opcodes that I'm missing, or my code dump is damaged in some way. 95% of my code seems to have disassembled correctly, but there's still some other quirks I can't quite account for.

If anyone has any insight, I'd appreciate it. This seems like it should be really simple, which is making me even more frustrated.

Seems to me that is just a compiler shortcut for gp=0xaaaabbbb such that it generates

movhi 0xaaaa, r0, gp
movea 0xbbbb, gp, gp

The sign extension comment is odd though, because it means if you try gp=0xaaaa8000, it will end up

movehi 0xaaaa, r0, gp
movea 0x8000, gp, gp

which will result in gp = 0xaaaa0000 + 0xffff8000 which is probably not what you want.

Still, 0x0000 is positive, so who knows.

Do the registers have a separate sign bit in this CPU?

NefMoto

Technical => Reverse Engineering => Topic started by: Jeff V. on June 15, 2017, 09:54:05 PM