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TC 1797 GPR addresses
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Topic: TC 1797 GPR addresses (Read 2450 times)
siado
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TC 1797 GPR addresses
« on: August 23, 2022, 07:41:37 PM »
Anyone working with TC1797 in Ghidra? Looking for opinion on A0, A1, A8, A9 addresses. Infineon user manual shows FF80, FF84, FFA0, and FFA4 as the offsets, but doesn't explicitly show the base address in that paragraph. I picked 0xF7E1 for the base address based on the SPB address map.
Ghidra seems to decompile functions correctly with it, but doesn't seem to have a problem with any random address I throw in there.
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nihalot
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Re: TC 1797 GPR addresses
« Reply #1 on: August 23, 2022, 10:22:06 PM »
search for "dsync" or "isync" and look at results, you'll see global regs getting loaded in SBOOT/CBOOT and ASW
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www.tangentmotorsport.com
multimap/LC/rolling antilag for MG1/MED17/EDC17/MED9/EDC15
contact for reverse engineering services of any ECU/TCU
prj
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Re: TC 1797 GPR addresses
« Reply #2 on: August 24, 2022, 03:33:35 AM »
Those registers are reserved for global variables.
It would help you tremendously if you understood C and the C compiler just a little... or at least read the TriCore EABI.
They are used for small data optimization, which is a code compression technique.
So it is not possible that they are contained in any address map, they will always be set at the entry point of the application. Of which as stated above are three.
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